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EN29GL128H/L
EN29GL128
128 Megabit (16384K x 8-bit / 8192K x 16-bit) Flash Memory Page mode Flash Memory, CMOS 3.0 Volt-only
FEATURES
* Single power supply operation - Full voltage range: 2.7 to 3.6 volts read and write operations * High performance - Access times as fast as 70 ns * VIO Input/Output 1.65 to 3.6 volts - All input levels (address, control, and DQ input levels) and outputs are determined by voltage on VIO input. VIO range is 1.65 to VCC * 8-word/16-byte page read buffer * 32-word/64-byte write buffer reduces overall programming time for multiple-word updates * Secured Silicon Sector region - 128-word/256-byte sector for permanent, secure identification - Can be programmed and locked by the customer * Uniform 64Kword/128KByte Sector Architecture One hundred twenty-eight sectors * Suspend and Resume commands for Program and Erase operations * Write operation status bits indicate program and erase operation completion * Support for CFI (Common Flash Interface) * Persistent methods of Advanced Sector Protection * WP#/ACC input - Accelerates programming time (when VHH is applied) for greater throughput during system production - Protects first or last sector regardless of sector protection settings * Hardware reset input (RESET#) resets device * Ready/Busy# output (RY/BY#) detects program or erase cycle completion * Minimum 100K program/erase endurance cycles. * Package Options - 56-pin TSOP - 64-ball 11mm x 13mm BGA * Industrial Temperature Range.
GENERAL DESCRIPTION
The EN29GL128 offers a fast page access time of 25 ns with a corresponding random access time as fast as 70 ns. It features a Write Buffer that allows a maximum of 32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time than standard programming algorithms. This makes the device ideal for today's embedded applications that require higher density, better performance and lower power consumption.
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CONNECTION DIAGRAMS Figure 1. 56-pin Standard TSOP (Top View)
RFU A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 RFU RFU 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RFU RFU A16 BYTE# Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0 RFU VIO
Note: RFU= Reserved for future use
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Figure 2. 64-ball Ball Grid Array (Top View, Balls Facing Down)
A8 RFU A7 A13 A6 A9 A5 WE# A4 RY / BY# A3 A7 A2 A3 A1 RFU
B8 A22 B7 A12 B6 A8 B5 RESET# B4 WP# / ACC B3 A17 B2 A4 B1 RFU
C8 RFU C7 A14 C6 A10 C5 A21 C4 A18 C3 A6 C2 A2 C1 RFU
D8 VIO D7 A15 D6 A11 D5 A19 D4 A20 D3 A5 D2 A1 D1 RFU
E8 VSS E7 A16 E6 DQ7 E5 DQ5 E4 DQ2 E3 DQ0 E2 A0 E1 RFU
F8 RFU F7
G8 RFU G7
H8 RFU H7 VSS H6 DQ6 H5 DQ4 H4 DQ3 H3 DQ1 H2 VSS H1 RFU
BYTE# DQ15 / A -1 F6 DQ14 F5 DQ12 F4 DQ10 F3 DQ8 F2 CE# F1 VIO G6 DQ13 G5 VCC G4 DQ11 G3 DQ9 G2 OE# G1 RFU
Note: RFU= Reserved for future use
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TABLE 1. PIN DESCRIPTION
Pin Name A22-A0 DQ0-DQ14 DQ15 / A-1 CE# OE# RESET# RY/BY# WE# Vcc Vss VIO BYTE# WP#/ACC RFU A22-A0 Data input/output. DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) Chip Enable Output Enable Hardware Reset Pin Ready/Busy Output Write Enable Supply Voltage (2.7-3.6V) Ground V I/O Input. Byte/Word mode selection Write Protect / Acceleration Pin ( WP# has an internal pull-up; when unconnected, WP# is at VIH.) Reserved for future use. Not Connected to anything
A0 - A22 DQ0 - DQ15 (A-1)
FIGURE 3. LOGIC DIAGRAM
EN29GL128
Function
CE# OE# WE# Reset# WP#/ACC Byte# VI O
RY/BY#
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Table 2. PRODUCT SELECTOR GUIDE
Product Number Speed Option Full Voltage Range: Vcc=2.7 - 3.6 V VIO=1.65 - 3.6 V EN29GL128 -70 70 25 70 25
Max Access Time, ns (tacc) Max Page Read Access, ns(tpacc) Max CE# Access, ns (tce) Max OE# Access, ns (toe)
BLOCK DIAGRAM
Vcc Vss VIO
RY/BY#
Block Protect Switch es
DQ0-DQ15 (A-1)
Erase Voltage Generator State Control Program Voltage Generator Chip Enable Output Enable Logic
STB
Input/Output Buffers
WE#
Command Register CE# OE#
Data Latch
Y-Decoder Address Latch
STB
Y-Gating
Vcc Detector
Timer
X-Decod er
Cell Matrix
A0-A22
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EN29GL128H/L Product Overview
EN29GL128 is 128 Mb, 3.0-volt-only, page mode Flash devices optimized for today's embedded designs that demand a large storage array and rich functionality. This product offers uniform 64 Kword (128 KB) uniform sectors and feature V I/O control, allowing control and I/O signals to operate from 1.65 V to VCC. Additional features include: * Single word programming or a 32-word buffer for an increased programming speed * Program Suspend/Resume and Erase Suspend/Resume * Advanced Sector Protection methods for protecting sectors as required * 128 words/256 bytes of Secured Silicon area for storing customer secured information. The Secured Silicon Sector is One Time Programmable.
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Table 3. Sector / Persistent Protection Sector Group Address Tables
PPB Group PPB 0 PPB 1 PPB 2 PPB 3 00000 A22-A18 Sector SA0 SA1 SA2 SA3 SA4 PPB 4 00001 SA5 SA6 SA7 SA8 PPB 5 00010 SA9 SA10 SA11 SA12 PPB 6 00011 SA13 SA14 SA15 SA16 PPB 7 00100 SA17 SA18 SA19 SA20 PPB 8 00101 SA21 SA22 SA23 SA24 PPB 9 00110 SA25 SA26 SA27 SA28 PPB 10 00111 SA29 SA30 SA31 SA32 PPB 11 01000 SA33 SA34 SA35 SA36 PPB 12 01001 SA37 SA38 SA39 PPB 13 01010 SA40 7 Sector Size (Kbytes / Kwords) 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64
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Address Range (h) Word mode (x16) 000000-00FFFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF 100000-10FFFF 110000-11FFFF 120000-12FFFF 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1FFFFF 200000-20FFFF 210000-21FFFF 220000-22FFFF 230000-23FFFF 240000-24FFFF 250000-25FFFF 260000-26FFFF 270000-27FFFF 280000-28FFFF
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SA41 SA42 SA43 SA44 PPB 14 01011 SA45 SA46 SA47 SA48 PPB 15 01100 SA49 SA50 SA51 SA52 PPB 16 01101 SA53 SA54 SA55 SA56 PPB 17 01110 SA57 SA58 SA59 SA60 PPB 18 01111 SA61 SA62 SA63 SA64 PPB 19 10000 SA65 SA66 SA67 SA68 PPB 20 10001 SA69 SA70 SA71 SA72 PPB 21 10010 SA73 SA74 SA75 SA76 PPB 22 10011 SA77 SA78 SA79 SA80 PPB 23 10100 SA81 SA82 SA83
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64
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290000-29FFFF 2A0000-2AFFFF 2B0000-2BFFFF 2C0000-2CFFFF 2D0000-2DFFFF 2E0000-2EFFFF 2F0000-2FFFFF 300000-30FFFF 310000-31FFFF 320000-32FFFF 330000-33FFFF 340000-34FFFF 350000-35FFFF 360000-36FFFF 370000-37FFFF 380000-38FFFF 390000-39FFFF 3A0000-3AFFFF 3B0000-3BFFFF 3C0000-3CFFFF 3D0000-3DFFFF 3E0000-3EFFFF 3F0000-3FFFFF 400000-40FFFF 410000-41FFFF 420000-42FFFF 430000-43FFFF 440000-44FFFF 450000-45FFFF 460000-46FFFF 470000-47FFFF 480000-48FFFF 490000-49FFFF 4A0000-4AFFFF 4B0000-4BFFFF 4C0000-4CFFFF 4D0000-4DFFFF 4E0000-4EFFFF 4F0000-4FFFFF 500000-50FFFF 510000-51FFFF 520000-52FFFF 530000-53FFFF
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SA84 PPB 24 10101 SA85 SA86 SA87 SA88 PPB 25 10110 SA89 SA90 SA91 SA92 PPB 26 10111 SA93 SA94 SA95 SA96 PPB 27 11000 SA97 SA98 SA99 SA100 PPB 28 11001 SA101 SA102 SA103 SA104 PPB 29 11010 SA105 SA106 SA107 SA108 PPB 30 11011 SA109 SA110 SA111 SA112 PPB 31 11100 SA113 SA114 SA115 SA116 PPB 32 11101 SA117 SA118 SA119 SA120 PPB 33 11110 SA121 SA122 SA123 PPB 34 PPB 35 PPB 36 PPB 37 11111 SA124 SA125 SA126 SA127 9 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64
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540000-54FFFF 550000-55FFFF 560000-56FFFF 570000-57FFFF 580000-58FFFF 590000-59FFFF 5A0000-5AFFFF 5B0000-5BFFFF 5C0000-5CFFFF 5D0000-5DFFFF 5E0000-5EFFFF 5F0000-5FFFFF 600000-60FFFF 610000-61FFFF 620000-62FFFF 630000-63FFFF 640000-64FFFF 650000-65FFFF 660000-66FFFF 670000-67FFFF 680000-68FFFF 690000-69FFFF 6A0000-6AFFFF 6B0000-6BFFFF 6C0000-6CFFFF 6D0000-6DFFFF 6E0000-6EFFFF 6F0000-6FFFFF 700000-70FFFF 710000-71FFFF 720000-72FFFF 730000-73FFFF 740000-74FFFF 750000-75FFFF 760000-76FFFF 770000-77FFFF 780000-78FFFF 790000-79FFFF 7A0000-7AFFFF 7B0000-7BFFFF 7C0000-7CFFFF 7D0000-7DFFFF 7E0000-7EFFFF 7F0000-7FFFFF
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Rev. H, Issue Date: 2009/10/01
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Table 4. Device OPERATING MODES 128M FLASH USER MODE TABLE
DQ8-DQ15 BYTE# BYTE# = VBIL = VBIH DBOUT DQ8DQ14= DBIN High-Z, DQ15 = DBIN A-1
B B B B B
Operation Read Write Accelerated Program CMOS Standby Output Disable Hardware Reset
CE# L L L
0.3V
OE# L H H
WE# H L L X H X
RESET # H H H Vcc0.3V H L
WP#/AC C L/H (Note 1) VBHH H L/H L/H
A0A22 ABIN ABIN
B B
DQ0DQ7 DBOUT DBIN
B B
ABIN X X X
B
DBIN
B
VBcc
B
X H X
High-Z High-Z High-Z
High-Z High-Z High-Z
High-Z High-Z High-Z
L X
Notes: 1. Addresses are A22:A0 in word mode; A22:A-1 in byte mode. 2. If WP# = VIL, on the outermost sector remains protected. If WP# = VIH, the outermost sector is unprotected. WP# has an internal pull-up; when unconnected, WP# is at VIH. All sectors are unprotected when shipped from the factory (The Secured Silicon Sector can be factory protected depending on version ordered.) 3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm. Legend L = Logic Low = VIL, H = Logic High = VIH, VHH = 8.5-9.5V, X = Don't Care, AIN = Address In, DIN = Data In, DOUT = Data Out
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EN29GL128H/L USER MODE DEFINITIONS
Word / Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic `1', the device is in word configuration, DQ0-DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic `0', the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
VIO Control
The VIO allows the host system to set the voltage levels that the device generates and tolerates on all inputs and outputs (address, control, and DQ signals). VIO range is 1.65 to VCC. For example, a VIO of 1.65-3.6 volts allows for I/O at the 1.65 or 3.6 volt levels, driving and receiving signals to and from other 1.65 or 3.6 V devices on the same data bus.
Read
All memories require access time to output array data. In a read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive with the address on its inputs. The device defaults to reading array data after device power-up or hardware reset. To read data from the memory array, the system must first assert a valid address on A22-A0, while driving OE# and CE# to VIL. WE# must remain at VIH. All addresses are latched on the falling edge of CE#. Data will appear on DQ15-DQ0 after address access time (tACC), which is equal to the delay from stable addresses to valid output data.The OE# signal must be driven to VIL. Data is output on DQ15-DQ0 pins after the access time (tOE) has elapsed from the falling edge of OE#, assuming the tACC access time has been meet.
Page Read Mode
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 8 words/16 bytes. The appropriate page is selected by the higher address bits A22-A3. Address bits A2-A0 in word mode (A2 to A-1 in byte mode) determine the specific word within a page. The microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode accesses are obtained by keeping the "read-page addresses" constant and changing the "intra-read page" addresses.
Autoselect
The Autoselect mode provides manufacturer ID, Device identification, and sector protection information, through identifier codes output from the internal register (separate from the memory array) on DQ7DQ0. The device only support to use autoselect command to access autoselect codes. It does not support to apply VID on address pin A9.
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* The Autoselect command sequence may be written to an address within a sector that is either in the read or erase-suspend-read mode. * The Autoselect command may not be written while the device is actively programming or erasing. * The system must write the reset command to return to the read mode (or erase-suspend-read mode if the sector was previously in Erase Suspend). * When verifying sector protection, the sector address must appear on the appropriate highest order address bits. The remaining address bits are don't care and then read the corresponding identifier code on DQ15-DQ0.
Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. During a write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. The Accelerated Program mode allows the host system to send program commands to the Flash device without first writing unlock cycles within the command sequence. Note the following: * When the Embedded Program algorithm is complete, the device returns to the read mode. * The system can determine the status of the program operation by reading the DQ status bits. Refer to the Write Operation Status on page 22 for information on these status bits. * An "0" cannot be programmed back to a "1." A succeeding read shows that the data is still "0." * Only erase operations can convert a "0" to a "1." * Any commands written to the device during the Embedded Program/Erase are ignored except the Suspend commands. * Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress. * A hardware reset and/or power removal immediately terminates the Program/Erase operation and the Program/Erase command sequence should be reinitiated once the device has returned to the read mode to ensure data integrity. * Programming is allowed in any sequence and across sector boundaries for single word programming operation. * Programming to the same word address multiple times without intervening erases is permitted.
Single Word Programming
Single word programming mode is one method of programming the Flash. In this mode, four Flash command write cycles are used to program an individual Flash address. The data for this programming operation could be 8 or 16-bits wide. While the single word programming method is supported by most devices, in general Single Word Programming is not recommended for devices that support Write Buffer Programming. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by reading the DQ status bits. * During programming, any command (except the Suspend Program command) is ignored. * The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress. * A hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. * Programming to the same address multiple times continuously (for example, "walking" a bit within a word) is permitted.
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Figure 4. Single Word Program
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Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard "word" programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming occurs. At this point, the system writes the number of "word locations minus 1" that are loaded into the page buffer at the Sector Address in which programming occurs. This tells the device how many write buffer addresses are loaded with data and therefore when to expect the "Program Buffer to Flash" confirm command. The number of locations to program cannot exceed the size of the write buffer or the operation aborts. (Number loaded = the number of locations to program minus 1. For example, if the system programs 6 address locations, then 05h should be written to the device.) The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the "write-buffer-page" address. All subsequent address/data pairs must fall within the elected-write-buffer-page. The "write-buffer-page" is selected by using the addresses A22-A5. The "write-buffer-page" addresses must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple "write-bufferpages." This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected "write-buffer-page", the operation ABORTs.) After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Note that if a Write Buffer address location is loaded multiple times, the "address/data pair" counter is decremented for every data load operation. Also, the last data loaded at a location before the "Program Buffer to Flash" confirm command is the data programmed into the device. It is the software's responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the "Program Buffer to Flash" command at the Sector Address. Any other address/data write combinations abort the Write Buffer Programming operation. The Write Operation Status bits should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then check the write operation status at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer "embedded" programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device returns to READ mode. The Write Buffer Programming Sequence is ABORTED under any of the following conditions: * Load a value that is greater than the page buffer size during the "Number of Locations to Program" step. * Write to an address in a sector different than the one specified during the Write-Buffer-Load command. * Write an Address/Data pair to a different write-buffer-page than the one selected by the "Starting Address" during the "write buffer data loading" stage of the operation. * Writing anything other than the Program to Buffer Flash Command after the specified number of "data load" cycles. The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the "last address location loaded"), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was ABORTED. Note that the Secured Silicon sector, autoselect, and CFI functions are unavailable when a program
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operation is in progress. Write buffer programming is allowed in any sequence of memory (or address) locations. These flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. Use of the write buffer is strongly recommended for programming when multiple words are to be programmed.
Figure 5. Write Buffer Programming Operation
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Sector Erase
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. Once the sector erase operation has begun, only the Sector Erase Suspend command is valid. All other commands are ignored. If there are several sectors to be erased, Sector Erase Command sequences must be issued for each sector. That is, only a sector address can be specified for each Sector Erase command. Users must issue another Sector Erase command for the next sector to be erased after the previous one is completed. When the Embedded Erase algorithm is completed, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to "Write Operation Status" for information on these status bits. Flowchart 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.
Figure 6. Sector Erase Operation
START
Write Erase Command Sequence
Data Poll from System or Toggle Bit successfully completed
Data =FFh? No Yes Erase Done
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Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 13. These commands invoke the Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory to an all zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip contain FFFFh. The system is not required to provide any controls or timings during these operations. When the Embedded Erase algorithm is complete, that sector returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to "Write Operation Status" for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that sector has returned to reading array data, to ensure the entire array is properly erased.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The sector address is required when writing this command. This command is valid only during the sector erase operation. The Sector Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Addresses are don't-cares when writing the Sector Erase Suspend command. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. After an erase-suspended program operation is complete, the device returns to the erase-suspendread mode. The system can determine the status of the program operation using write operation status bits, just as in the standard program operation. In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. Refer to Write Buffer Programming and the Autoselect for details. To resume the sector erase operation, the system must write the Erase Resume command. The address of the erase-suspended sector is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming operation or a "Write to Buffer" programming operation so that data can read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation within 15 s maximum (5 s typical) and updates the status bits. Addresses are "don't-cares" when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any nonsuspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not within a sector in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area, then user must use the proper command sequences to enter and exit this region.
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The system may also write the Autoselect Command Sequence when the device is in Program Suspend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the Autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the write operation status bits, just as in the standard program operation. The system must write the Program Resume command (address bits are "don't care") to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming.
Accelerated Program
Accelerated single word programming and write buffer programming operations are enabled through the WP#/ACC pin. This method is faster than the standard program command sequences. If the system asserts VHH on this input, the device automatically enters the Accelerated Program mode and uses the higher voltage on the input to reduce the time required for program operations. The system can then use the Write Buffer Load command sequence provided by the Accelerated Program mode. Note that if a "Write-to-Buffer-Abort Reset" is required while in Accelerated Program mode, the full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the ACC input, upon completion of the embedded program operation, returns the device to normal operation. * Sectors must be unlocked prior to raising WP#/ACC to VHH. * The WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. * It is recommended that WP#/ACC apply VHH after power-up sequence is completed. In addition, it is recommended that WP#/ACC apply from VHH to VIH/VIL before powering down VCC/ VIO .
Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last word being programmed in the write-buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other than the last word to be programmed in the writebuffer-page returns false status information. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# polling on DQ7 is active, then that sector returns to the read mode. During the Embedded Erase Algorithm, Data# polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7.
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After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00 appears on successive read cycles.
Figure 7. Write Operation Status Flowchart
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any
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address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address that is being programmed or erased causes DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase 2suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7. If a program address falls within a protected sector, DQ6 toggles for approximately 1s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program Algorithm is complete. Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the change in state.
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erasesuspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information.
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erases operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high. If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Note When verifying the status of a write operation (embedded program/erase) of a memory sector, DQ6 and DQ2 toggle between high and low states in a series of consecutive and contiguous status read cycles. In order for this toggling behavior to be properly observed, the consecutive status bit reads must not be interleaved with read accesses to other memory sectors. If it is not possible to temporarily prevent reads to other memory sectors, then it is recommended to use the DQ7 status bit as the alternative method of determining the active or inactive status of the write operation.
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DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device does not output a 1 on DQ5 if the system tries to program a 1 to a location that was previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device ignores the bit that was incorrectly instructed to be programmed from a 0 to a 1, while any other bits that were correctly requested to be changed from 1 to 0 are programmed. Attempting to program a 0 to a 1 is masked during the programming operation. Under valid DQ5 conditions, the system must write the reset command to return to the read mode (or to the erasesuspend-read mode if a sector was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator
After writing a sector erase command sequence, the output on DQ3 can be checked to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) When sector erase starts, DQ3 switches from "0" to "1". This device does not support multiple sector erase (continuous sector erase) command sequences so it is not very meaningful since it immediately shows as a "1" after the first 30h command. Future devices may support this feature.
DQ1: Write to Buffer Abort
DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a "1". The system must issue the "Write to Buffer Abort Reset" command sequence to return the device to reading array data.
Table 5. Write Operation Status
Status Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Program Suspend Read Erase Suspend Read Program Suspended Sector Non-Program Suspended Sector Erase Suspended Sector Non-Erase Suspended Sector DQ7 (note 2) DQ7# 0 DQ6 Toggle Toggle DQ5 (note 1) 0 0 DQ3 N/A 1 DQ2 (note 2) No Toggle Toggle DQ1 0 N/A RY/BY# 0 0 1 1 N/A Toggle N/A 1 0 N/A N/A N/A N/A N/A N/A N/A 0 1 0 0 0
Program Suspend Mode
Invalid (Not allowed) Data 1 No Toggle 0 Data DQ7# DQ7# DQ7# Toggle Toggle Toggle 0 0 0
Erase Suspend Mode
Erase Suspend Program (Embedded Program) Busy(note 3) Abort(note 4)
Write to Buffer
Notes 1. DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location. 4. DQ1 switches to 1 when the device has aborted the write-to-buffer operation
Writing Commands/Command Sequences
During a write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector or the entire device. Table 3 indicates the address space that each sector occupies. The device address
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space is divided into uniform 64KW/128KB sectors. A sector address is the set of address bits required to uniquely select a sector. ICC2 in "DC Characteristics" represents the active current specification for the write mode. "AC Characteristics" contains timing specification tables and timing diagrams for write operations.
RY/BY#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. This feature allows the host system to detect when data is ready to be read by simply monitoring the RY/BY# pin, which is a dedicated output and controlled by CE# (not OE#).
Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP (RESET# Pulse Width), the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. To ensure data integrity Program/Erase operations that were interrupted should be reinitiated once the device is ready to accept another command sequence. When RESET# is held at VSS, the device draws VCC reset current (ICC5). If RESET# is held at VIL, but not at VSS, the standby current is greater. RESET# may be tied to the system reset circuitry which enables the system to read the boot-up firmware from the Flash memory upon a system reset.
Software Reset
Software reset is part of the command set that also returns the device to array read mode and must be used for the following conditions: 1. To exit Autoselect mode 2. When DQ5 goes high during write status operation that indicates program or erase cycle was not successfully completed 3. Exit sector lock/unlock operation. 4. To return to erase-suspend-read mode if the device was previously in Erase Suspend mode. 5. After any aborted operations The following are additional points to consider when using the reset command: * This command resets the sectors to the read and address bits are ignored. * Reset commands are ignored during program and erase operations. * The reset command may be written between the cycles in a program command sequence before programming begins (prior to the third cycle). This resets the sector to which the system was writing to the read mode. * If the program command sequence is written to a sector that is in the Erase Suspend mode, writing the reset command returns that sector to the erase-suspend-read mode. * The reset command may be written during an Autoselect command sequence. * If a sector has entered the Autoselect mode while in the Erase Suspend mode, writing the reset command returns that sector to the erase-suspend-read mode. * If DQ1 goes high during a Write Buffer Programming operation, the system must write the "Write to Buffer Abort Reset" command sequence to RESET the device to reading array data. The standard RESET command does not work during this condition.
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Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware methods, which are independent of each other. This section describes the various methods of protecting data stored in the memory array. An overview of these methods in shown in Figure 8.
Figure 8. Advanced Sector Protection/Unprotection
Lock Register
The Lock Register consists of 4 bits. The Secured Silicon Sector Protection Bit is DQ0, Persistent Protection Mode Lock Bit is DQ1, Persistent Sector Protection OTP bit is DQ3 and DYB Lock Boot Bit is DQ4. If DQ0 is `0', it means that the Customer Secured Silicon area is locked and if DQ0 is `1', it means
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that it is unlocked. When DQ1 is set to `0', the device is used in the Persistent Protection Mode. DQ3 is programmed in the Eon factory. When the device is programmed to disable all PPB erase command, DQ3 outputs a `0', when the lock register bits are read. Similarly, if the device is programmed to enable all PPB erase command, DQ3 outputs a `1' when the lock register bits are read. Likewise the DQ4 bit is also programmed in the EON Factory. DQ4 is the bit which indicates whether Volatile Sector Protection Bit (DYB) is protected or not after boot-up. When the device is programmed to set all Volatile Sector Protection Bit protected after power-up, DQ4 outputs a `0' when the lock register bits are read. Similarly, when the device is programmed to set all Volatile Sector Protection Bit unprotected after power-up, DQ4 outputs a `1'. Each of these bits in the lock register are non-volatile. DQ15- DQ5 are reserved and will be 1's.
Table 6. Lock Register
DQ15-5 DQ4 DQ3 PPB One Time Programmable Bit DQ2 Reserved DQ1 Persistent Protection Mode Lock Bit DQ0 Secured Silicon Sector Protection Bit
Reserved DYB Lock Boot Bit
0 = protected all 0 = All PPB Erase DYB after boot-up Command disabled (default = 1) 1 = unprotected all 1 = All PPB Erase DYB after boot-up Command enabled (default = 1) (default = 1)
0 = Persistent 0 = protected (default = 1) Protection enabled 1 = unprotect (default = 0) (default = 1)
Notes: 1. After the Lock Register Bits Command Set Entry command sequence is written, reads and writes for all Sector are disabled, while reads from other sectors are allowed until exiting this mode. 2. Only DQ0 could be change by Lock Register Bits Command for user. Others bits were set by Factory. After selecting a sector protection method, each sector can operate in any of the following three states: 1. Constantly locked: The selected sectors are protected and can not be reprogrammed unless PPB lock bit is cleared via hardware reset, or power cycle. 2. Dynamically locked: The selected sectors are protected and can be altered via software commands. 3. Unlocked: The sectors are unprotected and can be erased and/or programmed.
Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile. For Sector 0~3 and 124~127 have one PPB for each sectors and for Sector 4~123 have one PPB every four sectors (refer to Figure 8 and Table 3. Sector / Persistent Protection Sector Group Address Tables) and have the same endurances as the Flash memory. Preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring. Notes 1. Each PPB is individually programmed and all are erased in parallel. 2. While programming PPB for the four sectors and Data polling on programming PPB address, array data can not be read from any sectors. 3. Entry command disables reads and writes for all sectors selected. 4. Reads within that sector return the PPB status for that sector. 5. All Reads must be performed using the read mode. 6. The specific sector address are written at the same time as the program command. 7. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-out without programming or erasing the PPB. 8. There are no means for individually erasing a specific PPB and no specific sector address is required for this operation. 9. Exit command must be issued after the execution which resets the device to read mode and reenables reads and writes for all sectors. 10. The programming state of the PPB for given sectors can be verified by writing a PPB Status Read Command to the device as described by the flow chart shown in Figure 9. User only can use DQ6 and RY/BY# pin to detect programming status.
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Figure 9. PPB Program Algorithm
Note: BA = base address
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Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared (erased to "1"). By issuing the DYB Set or Clear command sequences, the DYBs are set (programmed to "0") or cleared (erased to "1"), thus placing each sector in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. Notes 1. The DYBs can be set (programmed to "0") or cleared (erased to "1") as often as needed. When the parts are first shipped, the PPBs are cleared (erased to "1") and upon power up or reset, the DYBs can be set or cleared depending upon the ordering option chosen. 2. If the option to clear the DYBs after power up is chosen, (erased to "1"), then the sectorsmay be modified depending upon the PPB state of that sector (see Table 7). 3. The sectors would be in the protected state If the option to set the DYBs after power up is chosen (programmed to "0"). 4. It is possible to have sectors that are persistently locked with sectors that are left in the dynamic state. 5. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected state of the sectors respectively. However, if there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates normally again. 6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP#/ACC = VIL. Note that the PPB and DYB bits have the same function when WP#/ACC = VHH as they do when ACC =VIH.
Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed to "0"), it locks all PPBs and when cleared (erased to "1"), allows the PPBs to be changed. There is only one PPB Lock Bit per device. Notes 1. No software command sequence unlocks this bit, but only a hardware reset or a power-up clears this bit. 2. The PPB Lock Bit must be set (programmed to "0") only after all PPBs are configured to the desired settings.
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Figure 10. Lock Register Program Algorithm
Advanced Sector Protection Software Examples Table 7. Sector Protection Schemes: DYB, PPB and PPB Lock Bit Combinations
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Table 7 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the sector. In summary, if the PPB Lock Bit is locked (set to "0"), no changes to the PPBs are allowed. The PPB Lock Bit can only be unlocked (reset to "1") through a hardware reset or power cycle. See also Figure 8 for an overview of the Advanced Sector Protection feature.
Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control: * When WP#/ACC is at VIL, the either the highest or lowest sector is locked (device specific). There are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. The following subsections describes these methods:
WP#/ACC Method
The Write Protect feature provides a hardware method of protecting one outermost sector. This function is provided by the WP#/ACC pin and overrides the previously discussed Sector Protection/Unprotection method. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the highest or lowest sector independently of whether the sector was protected or unprotected using the method described in Advanced Sector Protection/Unprotection on page 24. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. The WP#/ACC pin must be held stable during a command sequence execution. WP# has an internal pull-up; when unconnected, WP# is set at VIH. Note If WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse "Glitch Protection"
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
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Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC 0.3 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC4 in "DC Characteristics" represents the standby current specification
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system.
Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. When RESET# is held at VSS 0.3 V, the device draws ICC reset current (ICC5). If RESET# is held at VIL but not within VSS 0.3 V, the standby current is greater. RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. (With the exception of RY/BY#.)
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region. The Secured Silicon Sector is 128 words in length and all Secured Silicon reads outside of the 128-word address range returns invalid data. The Secured Silicon Sector Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. Please note the following general conditions: * On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. * Reads outside of sector SA0 return memory array data. * Sector SA0 is remapped from memory array to Secured Silicon Sector array. * Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command must be issued to exit Secured Silicon Sector Mode. * The Secured Silicon Sector is not accessible when the device is executing an Embedded Program Or Embedded Erase algorithm. * The ACC function is not available when the Secured Silicon Sector is enabled.
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Table 8. Secured Silicon Sector Addresses
Secured Silicon Sector Address Range 000000h-000007h 000008h-00007Fh Reserve for Factory Determined by customer
Customer Lockable Secured Silicon Sector
The Customer Lockable Secured Silicon Sector is always shipped unprotected (DQ0 set to "1"), allowing customers to utilize that sector in any manner they choose. If the security feature is not required, the Secured Silicon Sector can be treated as an additional Flash memory space. Please note the following: * Once the Secured Silicon Sector area is protected, the Secured Silicon Sector Indicator Bit (DQ0) is permanently set to "0." * The Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. The Secured Silicon Sector lock must be used with caution as once locked, there is no procedure available for unlocking the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. * The accelerated programming (ACC) is not available when the Secured Silicon Sector is enabled. * Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence which return the device to the memory array at sector 0. * The address 0h~7h in Secured Silicon Sector is reserved for Factory.
Secured Silicon Sector Entry/Exit Command Sequences
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Secured Silicon Sector Entry Command allows the following commands to be executed * Read customer and factory Secured Silicon areas * Program the customer Secured Silicon Sector After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the memory array. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device.
COMMON FLASH INTERFACE (CFI)
The common flash interface (CFI) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC IDindependent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 9~12.In word mode, the upper address bits (A7-MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 9~12. The system must write the reset command to return the device to the autoselect mode.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Table 9. CFI Query Identification String
Addresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
Table 10. System Interface String
Addresses (Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0003h 0004h 0009h 0000h 0005h 0005h 0004h 0000h Description Vcc Min (write/erase) DQ7-DQ4: volt, DQ3-DQ0: 100mV Vcc Max (write/erase) DQ7-DQ4: volt, DQ3-DQ0: 100mV Vpp Min voltage (00h = no Vpp pin present) Vpp Max voltage (00h = no Vpp pin present) Typical timeout per single byte/word write 2N s Typical timeout for min size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max timeout for byte/word write 2N times typical Max timeout for buffer write 2N times typical Max timeout per individual block erase 2N times typical Max timeout for full chip erase 2N times typical (00h = not supported)
Table 11. Device Geometry Definition
Addresses (Word mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h Data 0018h 0002h 0000h 0006h 0000h 0001h 007Fh 0000h 0000h 0002h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Description Device Size = 2N bytes. 2**24=16MB=128Mb Flash Device Interface Description (refer to CFI publication 100); 01h = X16 only; 02h = x8/x16 Max number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification of CFI publication 100) 128 uniform sectors (7Fh + 1)
Erase Block Region 3 Information (refer to the CFI specification of CFI publication 100)
Erase Block Region 3 Information (refer to the CFI specification of CFI publication 100)
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This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Rev. H, Issue Date: 2009/10/01
EN29GL128H/L
39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to the CFI specification of CFI publication 100)
Table 12. Primary Vendor-specific Extended Query
Addresses (Word Mode) 40h 41h 42h 43h 44h 45h 46h 47h 48h Data 0050h 0052h 0049h 0031h 0034h 000Ch 0002h 0001h 0000h Description Query Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 00 = Required, 01 = Not Required Technology (Bits 5-2) 0001 = 0.18um, 0010 = 0.13um, 0011 = 90nm Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Minimum number of sectors per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect Scheme 00h = High Voltage Sector Protection 01h = High Voltage + In-System Sector Protection 02h = HV + In-System + Software Command Sector Protection 03h = Software Command Sector Protection Simultaneous Operation 00 = Not Supported, X = Number of Sectors Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page Minimum WP#/ACC (Acceleration) Supply Voltage 00 = Not Supported, DQ7-DQ4: Volts, DQ3=DQ0: 100mV Maximum WP#/ACC (Acceleration) Supply Voltage 00 = Not Supported, DQ7-DQ4: Volts, DQ3=DQ0: 100mV Top/Bottom Boot Sector Flag 04 = Uniform sectors bottom WP# protect 05 = Uniform sectors top WP# protect Program Suspend 00 = Not Supported, 01 = Supported Accelerated Program (Unlock Bypass mode) 00 = Not Supported, 01 = Supported Secured Silicon Sector (Customer OTP Area) Size 2N bytes Hardware Reset Low Time-out during an embedded algorithm to read mode Maximum 2N ns Hardware Reset Low Time-out not during an embedded algorithm to read mode Maximum 2N ns Erase Suspend Latency Maximum 2N s Program Suspend Latency Maximum 2N s Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks
49h
0003h
4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h
0000h 0000h 0002h 0085h 0095h 00xxh 0001h 0001h 0008h 000Fh 0009h 0005h 0005h 0000h
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Table 13. EN29GL128 Command Definitions
Command Sequence Read Reset Word Manufacturer ID Autoselect Byte Device ID Sector Protect Verify Program Write to Buffer Program Buffer to Flash Write to Buffer Abort Reset Chip Erase Sector Erase Word Byte Word Byte Word Byte Word 4 Byte Word Byte 4 6 1 3 6 6 1 1 3 4 1 2 AAA 555 AAA 555 SA 555 555 AAA 555 AAA XXX XXX 555 555 55 AA XX AA AA 29 AA AA AA B0 30 AA AA 98 A0 PA PD 2AA 2AA 55 55 555 555 88 90 XX 00 2AA 2AA 555 2AA 555 55 55 55 555 555 AAA 555 AAA F0 80 80 555 AAA 555 AAA AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 4 4 AAA 555 AAA 555 AA 555 2AA 555 2AA 55 55 AA
Cycles
Bus Cycles
Cycle Addr Data
P
1P
st
Cycle Addr Data
P
2P
nd
Cycle Addr Data
P
3P
rd
4P Cycle
P
th
5P Cycle
P
th
6P
th
P
Addr
Data
Addr
Data
Addr
Cycle Data
1 1
RA XXX 555
RD F0 2AA AA 555 2AA 555 2AA 55 AAA 555 AAA SA A0 25 55 55 AAA 555 AAA 555 90 90 555 90 000 100 000 200 X01 X02 (SA) X02 (SA) X04 PA SA 7F 1C 7F 1C 227E
7E
X0E X1C
2221
21
X0F X1E
2201
01
00 01 00 01 PD WC PA PD
WBL
PD
Erase/Program Suspend Erase/Program Resume Secured Silicon Sector Entry Secured Silicon Sector Exit Word CFI Query Byte Accelerated Program
Legend X = Don't care RA = Address of the memory to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax-A16 uniquely select any sector. WBL = Write Buffer Location. The address must be within the same write buffer page as PA. WC = Word Count is the number of write buffer locations to load minus 1.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29GL128H/L
Table 14. EN29GL128 Command Definitions
Command Sequence
Lock Register
Cycles
Bus Cycles
Cycle Addr Data
P
1P
st
Cycle Addr Data
P
2P
nd
Cycle Addr Data
P
3P
rd
4P Cycle
P
th
5P Cycle
P
th
6P
th
P
Addr
Data
Addr
Data
Addr
Cycle Data
Command Set Entry Program Read Command Set Exit PPB Command Set Entry PPB Program All PPB Erase PPB Status Read
Word Byte
3 3 2 1 2
555 AAA XXX 00 XXX 555 AAA XXX XXX SA XXX 555 AAA XXX XXX XXX 555 AAA XXX XXX SA XXX
AA AA A0 RD 90 AA AA A0 80 RD 90 AA AA A0 RD 90 AA AA A0 A0 RD 90
2AA 55 XXX XXX 2AA 55 SA 00 XXX 2AA 555 XXX
55 55
Data
555 AAA
40 40
00 55 55 00 30 00 55 55 00 555 AAA 50 50 555 AAA C0 C0
Word Byte
3 3 2 2 1 2 3 3 2 1 2 3 3 2 2 1 2
Global Non-Volatile
PPB Command Set Exit Volatile Freeze PPB Lock Command Set Entry PPB Lock Set Word Byte
Global
PPB Lock Status Read PPB Lock Command Set Exit DYB Command Set Entry Word Byte
XXX 2AA 555 SA SA XXX
00 55 55 00 01 00 555 AAA E0 E0
Volatile
DYB Set DYB Clear DYB Status Read DYB Command Set Exit
Legend X = Don't care RD(0) = Read data. SA = Sector Address. Address bits Amax-A16 uniquely select any sector. PWD = Password PWDx = Password word0, word1, word2, and word3. Data = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit, PD(1) = Persistent Protection Mode Lock Bit, PD(2) = Password Protection Mode Lock Bit.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29GL128H/L
Table 15. DC Characteristics
(Ta = - 40C to 85C; VCC = 2.7-3.6V) Symbol ILI ILO ICC1 IIO2 ICC2 ICC3 ICC4 ICC5 ICC6 IACC VIL VIH VHH VOL VOH VLKO Parameter Input Leakage Current Output Leakage Current VCC Active Read Current VIO Non-Active Output VCC Intra-Page Read Current VCC Active Erase/ Program Current VCC Standby Current VCC Reset Current Automatic Sleep Mode ACC Accelerated Program Current Input Low Voltage Input High Voltage Acceleration Program Voltage Output Low Voltage Output High Voltage CMOS Supply voltage (Erase and Program lock-out) IOL = 100A IOH = -100A 0.85 x VIO 2.3 2.5 Test Conditions 0V VIN Vcc 0V VOUT Vcc CE# = VIL; OE# = VIH ; VCC = VCC max 5MHz 10MHz 15 25 0.2 1 5 20 1.5 1.5 1.5
WP#/ACC pin VCC pin
Min
Typ
Max 5 1 30 45 10 10
Unit A A mA mA mA mA
CE# = VIL , OE# = VIH CE# = VIL , OE# = VIH , VCC = VCCmax, f = 10 MHz CE# = VIL , OE# = VIH , VCC = VCCmax, f = 33 MHz CE# = VIL , OE# = VIH , VCC = VCCmax CE#, RESET# = VCC 0.3 V, OE# = VIH , VCC = VCC max VIL = Vss + 0.3 V/-0.1V, RESET# = Vss 0.3V VIH = Vcc 0.3V VIL = Vss 0.3V
CE# = VIL, OE# = VIH, VCC = VCCmax, WP#/ACC = VHH
15 30 10 10 10 10 30 0.3 x VIO VIO + 0.3 9.5 0.15 x VIO mA A A A mA V V V V V V
3 15 -0.5 0.7 x VIO 8.5
Notes: 1. BYTE# pin can also be GND 0.3V. BYTE# and RESET# pin input buffers are always enabled so that they draw power if not at full CMOS supply voltages. 2. Maximum ICC specifications are tested with Vcc = Vcc max. 3. Not 100% tested.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29GL128H/L
Figure 11. Test Conditions
Table 16. Test Specifications
Test Conditions Output Load Capacitance, CBL
B
-70 30 5 0.0-3.0 1.5 1.5
Unit pF ns V V V
Input Rise and Fall times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29GL128H/L
AC CHARACTERISTICS Table 17. Read-only Operations Characteristics
Parameter Symbols JEDEC Standard Description Read Cycle Time Address to Output Delay Chip Enable To Output Delay Page Access Time Output Enable to Output Delay Chip Enable to Output High Z Output Enable to Output High Z Output Hold Time from Addresses, CE# or OE#, whichever occurs first Output Enable Hold Time Read Toggle and DATA# Polling CE# = VIL OE#= VIL OE#= VIL Test Setup Min Max Max Max Max Max Max Min Min Min Speed -70 70 70 70 25 25 20 20 0 0 10 ns ns ns ns ns ns ns ns ns ns Unit
tAVAV tAVQV tELQV
tRC tACC tCE tPACC
tGLQV tEHQZ tGHQZ tAXQX
tOE tDF tDF tOH tOEH
Notes: 1. High Z is Not 100% tested. 2. For - 70 Vcc = 2.7V - 3.6V Output Load : 1 TTL gate and 30pF Input Rise and Fall Times: 5ns Input Rise Levels: 0.0 V to 3.0 V Timing Measurement Reference Level, Input and Output: 1.5 V
Figure 12. AC Waveforms for READ Operations tBRCB
Addresses CE#
Addresses Stable
tBACC tBOEB tBOEHB tBDF
OE#
WE#
tBCEB
HIGH Z Output Valid
tBOH
HIGH Z
Outputs RESET#
RY/BY#
0V
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Figure 13. Page Read Operation Timings
Note: Addresses are A2:A-1 for byte mode.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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AC CHARACTERISTICS Table 18. Hardware Reset (RESET#)
Paramete r Std tRP1 tRP2 tRH tRB1 tRB2 tREADY1 tREADY2 Description
RESET# Pulse Width (During Embedded Algorithms) RESET# Pulse Width (NOT During Embedded Algorithms) Reset# High Time Before Read RY/BY# Recovery Time ( to CE#, OE# go low) RY/BY# Recovery Time ( to WE# go low) Reset# Pin Low (During Embedded Algorithms) to Read or Write Reset# Pin Low (NOT During Embedded Algorithms) to Read or Write
Test Setup Min Min Min Min Min Max Max
Speed -70 10 500 50 0 50 20 500
Unit us ns ns ns ns us ns
Figure 14. AC Waveforms for RESET# Reset# Timings
tRB1 CE#, OE# WE# tREADY1 tRB2
RY/BY# RESET#
tRP1 Reset Timing during Embedded Algorithms CE#, OE# tRH
RY/BY# RESET# tRP2 tREADY2 Reset Timing NOT during Embedded Algorithms
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29GL128H/L
AC CHARACTERISTICS Table 19. Word / Byte Configuration (BYTE#)
Std Parameter tBCS tCBH tRBH
Test Setup
Speed -70 0 0 0
Description Byte# to CE# switching setup time CE# to Byte# switching hold time RY/BY# to Byte# switching hold time
Unit ns ns ns
Min Min Min
Figure 15. AC Waveforms for BYTE#
CE#
OE#
Byte#
tBCS
tCBH
Byte# timings for Read Operations
CE#
WE#
Byte# tBCS RY/BY# Byte #timings for Write Operations
Note: Switching BYTE# pin not allowed during embedded operations
tRBH
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. H, Issue Date: 2009/10/01
EN29GL128H/L
AC CHARACTERISTICS Table 20. Write (Erase/Program) Operations
Parameter Symbols JEDEC Standard Description Min Min Min Min Min MIn Min Min Min Min Min Min Typ Typ Max Typ Sector Erase Operation Max Typ Min Min Max Min Speed -70 Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Toggle and DATA# Polling Read Recovery Time before Write (OE# High to WE# Low) Output Enable Hold Time CE# SetupTime CE# Hold Time Write Pulse Width Write Pulse Width High Write Buffer Program Operation (Note 2, 3) Programming Operation (Word and Byte Mode) 70 0 45 30 0 0 10 0 0 0 35 20 160 8 200 0.1 2 30 250 50 70 0 ns ns ns ns ns ns ns ns ns ns ns ns s s s s s s ns s ns ns
Unit
tAVAV tAVWL tWLAX tDVWH tWHDX
tWC tAS tAH tDS tDH tOEH
tGHWL tELWL tWHEH tWLWH tWHDL tWHWH1
tGHWL tCS tCH tWP tWPH tWHWH1
tWHWH2 tWHWH3
tWHWH2 tWHWH3 tVHH tVCS tBBUSY tRB
Chip Erase Operation VHH Rise and Fall Time Vcc Setup Time WE# High to RY/BY# Low Recovery Time from RY/BY#
Notes: 1. Not 100% tested. 2. See table.22 Erase and Programming Performance for more information. 3. For 1~32 words bytes programmed.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29GL128H/L
AC CHARACTERISTICS Table 21. Write (Erase/Program) Operations
Alternate CE# Controlled Writes Parameter Symbols JEDEC Standard
Description Min Min Min Min Min Min Min Min Min Min Typ Typ Max Typ
Speed -70
Unit ns ns ns ns ns ns ns ns ns ns s s s s s
tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1
tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1
Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time before Write (OE# High to CE# Low) WE# SetupTime WE# Hold Time Write Pulse Width Write Pulse Width High Write Buffer Program Operation (Note 2, 3) Programming Operation (Word and Byte mode)
70 0 45 30 0 0 0 0 35 20 160 8 200 0.1 2
tWHWH2
tWHWH2
Sector Erase Operation
Max
Notes: 1. Not 100% tested. 2. See table.22 Erase and Programming Performance for more information. 3. For 1~32 words bytes programmed.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29GL128H/L AC CHARACTERISTICS
Figure 16. AC Waveforms for Chip/Sector Erase Operations Timings
Erase Command Sequence (last 2 cycles) Read Status Data (last two cycles)
tWC
Addresses
tAS SA
tAH VA
0x555 for chip erase
0x2AA
VA
CE#
tGHW
OE#
tCH tWP
WE#
tCS
tWP
tWHWH2 or tWHWH3
Data
0x55 tDS tDH
0x30
tBUS
Status
DOUT
tRB
RY/BY#
VCC
tVCS
Notes: 1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, Dout=true data at read address. 2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command sequence.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29GL128H/L
Figure 17. Program Operation Timings
Program Command Sequence (last 2 cycles) Program Command Sequence (last 2 cycles)
tWC
Addresses CE# 0x555
tAS
PA
tAH
PA PA
tGHWL
OE#
tCH tWP tCS tWPH
OxA0 PD
WE#
tWHWH1
Status DOUT
Data
tDS
RY/BY#
tDH
tBUSY
tRB
tVCS VCC
Notes: 1. PA=Program Address, PD=Program Data, DOUT is the true data at the program address. 2. VCC shown in order to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29GL128H/L
Figure 18. AC Waveforms for /DATA Polling During Embedded Algorithm Operations
tRC
Addresses
tCH
VA tACC tCE
VA
VA
CE#
tOE
OE#
tOEH
tDF
WE#
tOH
DQ[7]
Complement
Complement
True
Valid Data
DQ[6:0]
tBUSY
Status Data
Status Data
True
Valid Data
RY/BY#
Notes: 1. VA=Valid Address for reading Data# Polling status data 2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.
Figure 19. AC Waveforms for Toggle Bit During Embedded Algorithm Operations
tRC
Addresses
tCH
VA
tACC tCE
VA
VA
VA
CE#
tOE
OE#
tOEH
tDF
WE#
tOH
DQ6, DQ2
tBUSY
Valid Status (first read)
Valid Status (second d)
Valid Status (stops toggling)
Valid Data
RY/BY#
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29GL128H/L
Figure 20. Alternate CE# Controlled Write Operation Timings
0x555 for Program 0x2AA for Erase PA for Program SA for Sector Erase 0x555 for Chip Erase
Addresses tWC WE# tGHEL OE# tWS CE# tDS Data
0xA0 for Program
PD for Program 0x30 for Sector Erase 0x10 for Chip Erase
VA
tAS
tAH
tWH tCP
tCPH
tCWHWH1 / tCWHWH2 / tCWHWH3
tDH
tBUSY Status DOUT
RY/BY# tRH Reset#
Notes: PA = address of the memory location to be programmed. PD = data to be programmed at byte address. VA = Valid Address for reading program or erase status Dout = array data read at VA Shown above are the last two cycles of the program or erase command sequence and the last status read cycle Reset# shown to illustrate tRH measurement references. It cannot occur as shown during a valid command sequence.
Figure 21. DQ2 vs. DQ6
Enter Embedded Erase Erase Suspend Enter Erase Suspend Program Enter Suspend Read Enter Suspend Program Erase Resume
WE#
Erase
Erase Suspend Read
Erase
Erase Complete
DQ6
DQ2
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. H, Issue Date: 2009/10/01
EN29GL128H/L
TABLE 22. ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Chip Programming Time Byte Word Typ 0.1 30 8 8 134.4 67.2 160 60 100K Limits Max 2 120 200 200 403.2 201.6 Unit sec sec s s sec Excludes system level overhead Comments Excludes 00h programming prior to erasure
Total Write Buffer time ACC Total Write Buffer time Erase/Program Endurance
s cycles Minimum 100K cycles
Notes: 1. Typical program and erase times assume the following conditions: room temperature, 3V and checkboard pattern programmed. 2. Maximum program and erase times assume the following conditions: worst case Vcc, 90C and 100,000 cycles.
Table 23. 56-PIN TSOP PIN CAPACITANCE @ 25C, 1.0MHz
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF
Note: Test conditions are Temperature = 25C and f = 1.0 MHz.
Table 24. DATA RETENTION
Parameter Description Data Retention Time Test Conditions 150C 125C Min 10 20 Unit Years Years
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Plastic Packages Ambient Temperature With Power Applied Output Short Circuit CurrentP1
P
Value -65 to +150 -65 to +125 -55 to +125 200
P Pand
Unit C C C mA V V
OE#, RESET# WP#/ACCP2
P
-0.5 to + 9.5 -0.5 to Vcc+0.5
Voltage with Respect to Ground
All other pins 3
P P
Vcc
-0.5 to + 4.0
V
Notes: 1. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. 2. Minimum DC input voltage on OE#, RESET# and WP#/ACC pins is -0.5V. During voltage transitions, OE#, RESET# and WP#/ACC pins may undershoot VBss to -1.0V for periods of up to 50ns and to -2.0V for periods of up to 20ns. See figure below. Maximum DC input voltage on OE#, and RESET# is 8.5V which may overshoot to 9.5V for periods up to 20ns. 3. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may undershoot VBss to -1.0V for periods of up to 50ns and to -2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is VBcc + 0.5 V. During voltage transitions, outputs may overshoot to VBcc + 1.5 V for periods up to 20ns. See figure below. 4. Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability.
B B B B
RECOMMENDED OPERATING RANGESP1
Parameter Ambient Operating Temperature Industrial Devices
P
Value -40 to 85
Unit C
Operating Supply Voltage Vcc
1.
Full Voltage Range: 2.7 to 3.6V
V
Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Vcc +1.5V
Maximum Negative Overshoot Waveform
Maximum Positive Overshoot Waveform
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
49
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. H, Issue Date: 2009/10/01
EN29GL128H/L
FIGURE 22. 56L TSOP 14mm x 20mm package outline
SYMBOL
A A1 A2 D D1 E e b L R 0 0 Note : 1. Coplanarity: 0.1 mm
MIN. --0.05 0.95 --------0.17 0.5 0.08
DIMENSION IN MM NOR ----1.00 20.00 18.40 14.00 0.50 0.22 0.60 0.15 3
0
MAX 1.20 0.15 1.05 --------0.27 0.70 0.20 5
0
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
50
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. H, Issue Date: 2009/10/01
EN29GL128H/L
FIGURE 23. 64 ball Ball Grid Array (FBGA), 11 X13 mm, Pitch 1mm package outline
SYMBOL A A1 A2 D E D1 E1 e b
DIMENSION IN MM MIN. - -0.40 0.60 12.90 10.90 - -- -- -0.50 NOR - -0.50 0.66 13.00 11.00 7.00 7.00 1.00 0.60 MAX 1.40 0.60 0.76 13.10 11.10 - -- -- -0.70
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
51
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. H, Issue Date: 2009/10/01
EN29GL128H/L Purpose
Eon Silicon Solution Inc. (hereinafter called "Eon") is going to provide its products' top marking on ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the compositions of the ICs. Eon is still keeping the promise of quality for all the products with the same as that of Eon delivered before. Please be advised with the change and appreciate your kindly cooperation and fully support Eon's product family.
Eon products' New Top Marking
cFeon Top Marking Example:
cFeon
Part Number: XXXX-XXX Lot Number: XXXXX Date Code: XXXXX
For More Information
Please contact your local sales office for additional information about Eon memory solutions.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
52
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. H, Issue Date: 2009/10/01
EN29GL128H/L
ORDERING INFORMATION
EN29GL128 H 70 Z I P
PACKAGING CONTENT P = RoHS compliant
TEMPERATURE RANGE I = Industrial (-40C to +85C)
PACKAGE Z = 56-pin TSOP BA = 64-Ball Ball Grid Array (BGA) 1.0mm pitch, 11mm x 13mm package
SPEED 70 = 70ns
SECTOR for WRITE PROTECT (WP#/ACC=L) H = highest address sector protected L = lowest address sector protected
BASE PART NUMBER EN = Eon Silicon Solution Inc. 29GL = FLASH, 3V Page Mode Flash Memory 128 =128 Megabit (16M x 8 / 8M x 16)
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
53
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. H, Issue Date: 2009/10/01
EN29GL128H/L
Revisions List
Revision No
A B
Description
Preliminary 1.Add Sector for write protect selection in Ordering information 2.Modify PPB sector group in table 7 and Figure 7. 3. Modify sector erase descirption and Figure 6. 1. Add internal pull-up description for WP# pin in Table1 on Page 4 2. Add WP#/ACC, VIO pin in Figure3 on Page 4 3. Modify tOE from 30ns to 25ns in Table 17 on Page 40 and Page 5 4. Add Secured Silicon Sector Entry/Exit command in Table13 5. Modify typo from Sector Erase Suspend to Erase/Program Suspend, from Sector Erase Resume to Erase/Program resume in Table13 6. Modify package code for 56-pin TSOP from T to Z in ordering information on Page 54 7. Del table 22 and Figure 20 Temporary Sector Unprotect Timing table and Diagram and Figure 21.Sector Protect/Unprotect Timing Diagram 8. Modify Erase/Program performance in Table 20, 21 and 22. Chip erase time from 32 30sec typ and 280 120sec max. Add ACC and total write buffer time spec 9. Correct typo from Byte to Word on Page 7 10. Del tCEH in table 17 11. Modify DC Characteristics in table 15 VHH from 10.5~11.5V to 8.5~9.5V ICC1 5MHz 9 15mA typ, 10MHz 16 25mA typ ICC4, ICC5 and ICC6 1 1.5uA typ, 5 10uA max Add IIO2 and IACCspec 12. Del apply VID on address pin A9 to access autoselect codes function. ( Remove TABLE 5 and modify description Autoselect section for using High voltage to get Autoselect Codes ) 13. Modify A9 spec from 9.5V to Vcc+0.5V in ABSOLUTE MAXIMUM RATINGS 14. Modify CFI 4Ah, 4Fh description and data of 4Fh in table 12 1. Modify naming for DQ0 OTP Lock Bit to Secured Silicon Sector Protection Bit on Page 25 2. Modify Table.8 Secured Silicon Sector Address Range 000000h000007h from Determined by customer to Reserve for Factory 3. Add note "The address 0h~7h in Secured Silicon Sector is reserved for Factory" on Page 31 Update FIGURE 23. 64 ball Fortified Ball Grid Array (FBGA), 11 X13 mm, Pitch 1mm package outline on page 52 1. Modify from Sector 0 to all sectors in note 1 of Table 6 and note 2, 3 and note 9 of PPB section on page 25. 2. Add "User only can use DQ6 and RY/BY# pin to detect programming status" in note 10 on page26. Change the package code of 64-ball BGA on page 53.
Date
2009/01/23 2009/02/18
C
2009/5/12
D
2009/6/19
E F G H
2009/07/01 2009/7/14 2009/07/22
Correct typo in Table 20, " tBBUSY " from Min. to Max on page 42. 2009/10/01
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
54
(c)2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. H, Issue Date: 2009/10/01

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